?
VC bias through Constant current circuit
Select an NPN transistor with V CEO equal or higher
than the input voltage (Vin) plus any expected
transient voltage and capable of handling the
expected maximum power dissipation. Any NPN
transistor with V CEO ≥ 100V in a small foot print is
suitable. An exemplary NPN is FJV1845 from
Fairchild:
From the FJV1845 datasheet:
NPN Silicon Transistor
V CEO = 120V Collector-Emitter maximum voltage
I C = 50mA maximum collector current
h FE = 150 minimum at I C =3mA
V BE(sat) = 0.55V to 0.65V Base-Emitter saturation
voltage at 25°C
Select Zener Diode: Select the Zener diode with low
bias current, a Zener diode with V Z =10 in small foot
print is suitable for this application. An exemplary
Zener diode MM3Z10VST1 from ON Semiconductor
From the MM3Z10VST1 datasheet:
10V, 200mW Zener Diode
V Z = 9.80V to 10.2V Zener voltage range
I R = 10μ A will hold the Zener breakdown voltage
at 9.8V
Pd Q 2 ? 2 . 29 mA ? [ 60 V ? 11 V ? ( 9 . 8 V ? 0 . 7 V )] ? 91 . 37 mW
The transistor Power De-rating vs. temperature curve
in the manufacturer datasheet shows that the device
can operate up to 110°C.
Figure 18: PI2007 in high side +48V application, VC
R LIMIT ?
V Z _ MIN ? V BE ( on )
I VC _ MAX
?
9.8 V ? 0.7 V
2 . 1 mA
? 4 . 33 k ?
is biased through constant current circuit.
Fault Indication:
Or 4.32kΩ 1%
PI2007 SGND pin in this application is floating and
I B _ MAX ?
I C _ MAX
h FE _ MIN
?
3.5 mA
150
? 23 . 33 ? A
FT is referenced to SGND. The FT output can be
referenced to system return (RTN) by adding a level
shift circuit as shown in Figure 19.
Q1: 2SA1579T106R, 120V PNP transistor from
R Z Calculation:
Use 100μA as mini mum for the Zener diode reverse
leakage current and Q2 base current combined.
Rohm.
Q2: DTC114EET1G, 50V NPN with bias resistors from
ON semiconductor.
R Z ?
V in _ MIN ? V Z _ MAX
I Z ? I B _ MAX
?
36 V ? 10.2 V
100 ? A
? 258 k ?
D1: 30V general purpose diode.
Select R Z = 249kΩ 1%
V Z _ MAX ? V BE _ MIN 10 . 2 V ? 0 . 50 V
I C _ MAX ? ?
Maximum Q2 collector current:
R LIMIT _ MIN 4 . 32 k ? * 0 . 98
? 2 . 29 mA
Maximum Q2 power dissipation
Pd Q 2 ? I C _ MAX ? [ Vin MAX ? V VC ? CLM ? ( V Z _ MIN ? V EB _ MAX )]
Figure 19: FT level shift circuitry
Picor Corporation ? picorpower.com
PI2007
Rev 1.3
Page 15 of 19
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